eInfochips - ASIC RTL Design Engineer

Eximietas Design - Lead Design Verification Engineer

Architect/Lead - Design and Verification - SOC/IP, SystemVerilog/UVM, SOC, RISC-C, Semiconductor Domain

Tessolve - Manager - RTL Design

Swedium Global - Senior ASIC Verification Engineer - UVM/System Verilog

Tessolve - Lead RTL Design Engineer

Member of Technical Staff - Logic Design & Verification

Static Timing Analysis Engineer - PnR