Senior RTL Design Engineer - ASIC/SoC

Principal/Lead Design Verification Engineer - UVM/SoC

Senior Design Verification Engineer/Lead - UVM/AMBA Protocols

Design Verification Engineer - System Verilog

eInfochips - ASIC RTL Design Engineer

Architect/Lead - Design and Verification - SOC/IP, SystemVerilog/UVM, SOC, RISC-C, Semiconductor Domain

Staff Engineer/Senior Staff Engineer - RTL/SoC

Tessolve - Manager - RTL Design

Sykatiya Technologies - RTL Design Engineer - Verilog/ASIC

ASIC RTL Design Engineer - SoC Subsystem

Tessolve - Lead RTL Design Engineer

Swedium Global - Senior ASIC Verification Engineer - UVM/System Verilog

Member of Technical Staff - Logic Design & Verification