Senior/Staff Engineer, Physical Design (Clocking)

Location : Bangalore, India - Onsite

Experience : 6+ Years

Employment Type : Full-time

Job Overview :

We're looking for an experienced Senior/Staff Engineer, Physical Design (Clocking) to lead our clock design efforts across IP, CPU, and SoC teams. In this critical onsite role, you'll define comprehensive clocking strategies that achieve tight timing, power, and area goals. You'll collaborate extensively with RTL, Physical Design (PD), and power engineers to build robust, high-performance systems for cutting-edge technology nodes.

Key Responsibilities :

- Own the end-to-end clock architecture across complex SoCs, driving its definition and implementation.

- Define clocking strategies that effectively balance aggressive timing, power, and area targets.

- Collaborate extensively with RTL, Physical Design, and power teams to ensure seamless integration and achieve design goals.

- Design and implement clock tree synthesis (CTS) and comprehensive clock network designs.

- Apply expertise in timing closure, Clock Domain Crossing (CDC) analysis, and low-power design techniques within clocking architectures.

- Work on advanced technology nodes (5nm or below), making informed design choices shaped by process limitations and opportunities.

- Develop and utilize scripts to automate tasks and significantly improve engineering workflows.

- Troubleshoot and solve complex problems related to clocking, striving for increased efficiency and robustness in designs.

Required Skills & Qualifications :

- 6+ years of experience in physical design, with a strong focus on clocking.

- Strong background in clock tree synthesis and clock network design.

- Proficiency in working with timing closure, Clock Domain Crossing (CDC), and low-power design techniques.

- Demonstrated experience with advanced technology nodes (5nm or below).

- Ability to write scripts to automate tasks and improve engineering workflows.

- Experience with industry-standard tools such as Synopsys Fusion Compiler (FC) and ICC2.

- Proficiency in scripting languages including Python, Perl, or Tcl.

- A Bachelor's or Master's degree in Computer Engineering, or a related field.

What You Will Learn :

- How to architect clocking strategies that scale effectively across IP, CPU, and SoC designs.

- Advanced techniques to reduce power consumption and jitter while meeting aggressive Power, Performance, Area (PPA) targets.

- Ways to significantly improve design flows and reduce manual effort through intelligent automation.

- How to navigate and solve unique challenges specific to cutting-edge technology nodes.