Posted on: 16/07/2025
CPU Test Bench DV Engineer
Experience : 7+ Years
Employment Type : Full-time
Job Overview :
- Design, develop, and maintain parameterizable core and cluster testbench environments using C++ and Synthesizable SystemVerilog for a RISC-V CPU family.
- Build essential testbench components, including harnesses, checkers, transactors, models, and miscellaneous items like preloaders, trickbox, and randomization logic.
- Contribute to our C++ methodology framework which incorporates modern C++ features, specifically designed to ease the writing of testbench components (CVM - UVM for C++).
- Work with environments that are portable across various simulators (including open-source Verilator) and emulation platforms.
- Provide crucial support to the core and cluster Design Verification (DV) teams in bringing up new architectural and micro-architectural features.
- Develop innovative tools and solutions to simplify the debugging of simulation/emulation failures.
Required Experience & Qualifications :
- Proficiency in C++ and SystemVerilog (SV) programming languages.
- Good understanding of the fundamentals behind a Design Verification (DV) methodology, such as UVM.
- Solid understanding of software engineering concepts, including publisher-subscriber patterns, multi threaded programming, and co-routines.
- Knowledge of any CPU architecture (x86, ARM, RISC-V) and basic micro-architecture principles.
- Strong problem-solving skills and the ability to analyze issues across different layers of the abstraction stack, from high-level software code to low-level assembly programs and RTL implementation code.
- Excellent communication skills and a proven ability to work effectively in a team environment.
- Eagerness to learn and adapt to new challenges in a fast-paced, dynamic environment.
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Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1514448
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