Description:

Hiring: STA / Synthesis / Core Timing Analysis Engineer (8+ Years)

Company: Sykatiya Technology Pvt Ltd

Experience: 8+ Years

Location: Bangalore

Notice Period: Immediate to 30 Days

We are looking for an experienced STA / Synthesis Engineer with strong expertise in Core Timing Analysis and Timing Sign-off to join our growing VLSI team.

Key Responsibilities:

- Perform Static Timing Analysis (STA) for complex SoC/ASIC designs.

- Handle Core Timing Analysis including setup/hold closure.

- Work on timing constraints, timing ECOs, and timing sign-off activities.

- Perform RTL synthesis and timing optimization.

- Analyze and fix timing violations across multiple PVT corners and modes.

- Work closely with Physical Design, DFT, and Design teams for timing closure.

- Generate and analyze timing reports and improve design performance.

Required Skills:

- Strong experience in STA and Synthesis flows.

- Hands-on experience with tools such as:

- Synopsys PrimeTime

- Cadence Tempus

- Synopsys Design Compiler

- Strong understanding of:

- Timing constraints (SDC)

- Setup/Hold analysis

- Clock tree concepts

- Multi-mode multi-corner (MMMC) analysis

- Good understanding of ASIC design flow.

Preferred:

- Experience in advanced technology nodes.

- Strong debugging and scripting skills (TCL/Perl/Python).

How to Apply:

Interested candidates can share their updated resume at:

hemant@sykatiya.com

Notice Period: Immediate to 30 days preferred

hashtag#Hiring hashtag#VLSIJobs hashtag#STA hashtag#Synthesis hashtag#TimingAnalysis hashtag#SykatiyaTech hashtag#BangaloreJobs hashtag#Immediat hashtag#SpreadTheWord