Mirafra Technologies is looking for an experienced Senior Design Verification Engineer to join our semiconductor verification team. The ideal candidate will have strong expertise in SoC/IP verification, high-speed interface protocols, and processor-based system validation. This role involves end-to-end ownership of verification activities including planning, development, execution, debugging, and coverage closure.

Key Responsibilities :

- Develop detailed verification plans based on design and architecture specifications

- Build scalable and reusable SystemVerilog/UVM-based testbenches

- Perform block-level and SoC-level functional verification

- Verify high-speed interfaces such as PCIe

- Validate memory subsystems including DDR/LPDDR

- Work on processor-based systems with knowledge of x86 architecture

- Develop directed and constrained-random test cases

- Perform functional and code coverage analysis and drive coverage closure

- Debug complex simulation failures and root cause design issues

- Participate in design reviews and provide feedback from a verification perspective

- Collaborate closely with design, validation, and physical design teams

Required Technical Skills :

- Strong hands-on experience in PCIe protocol verification

- Solid understanding of SoC Verification methodologies

- Experience with DDR / LPDDR memory protocols

- Good knowledge of x86 architecture fundamentals

- Expertise in SystemVerilog and UVM methodology

- Experience in testbench architecture and debugging

- Understanding of assertions (SVA), coverage-driven verification

- Familiarity with simulation and debugging tools

Preferred / Good to Have Skills :

- Experience with regression management

- Knowledge of scripting languages such as Python or Shell

- Experience with emulation or FPGA-based verification

- Exposure to low-power verification concepts

- Understanding of AMBA protocols (AXI/AHB/APB)