RTL Design Engineer

Responsibilities :

- Develop synthesizable RTL for high-performance SoC, subsystem, or IP designs APB

- Contribute to architecture definition, micro-architecture design, and implementation

- Collaborate closely with architecture, verification, and physical design teams ARM

- Own and deliver RTL blocks from spec to tape-out

- Ensure clean handoff of RTL to verification and synthesis

- Support post-silicon bring-up and debugging, if required

Mandatory Requirements :

- 5-10 years of hands-on RTL design experience in production-grade projects

- At least 3 full-cycle design projects (preferably SoC, subsystem, or IP level)

- Strong expertise in Verilog/SystemVerilog RTL coding

- Solid understanding of digital design principles including clocking, resets, data-path control, pipelining, etc.

- Exposure to design closure flow including synthesis and timing closure support

- Familiarity with AMBA (AXI, AHB, APB) or similar interconnects

- Experience working in cross-functional engineering teams

- Good understanding of synthesis, STA, and backend interactions

- Strong problem-solving and debugging skills

- Excellent communication and documentation capabilities