Description:

Role: Lead SoC Verification Engineer (UVM / TB Architecture)

Experience: 8 to 15 Years

Location: Bangalore

Employment Type: Full-time / Contract (as applicable)

Role Summary:

We are seeking a hands-on Lead SoC Verification Engineer to own the end-to-end verification of complex SoCs or large subsystems. This role spans testbench architecture, verification strategy, coverage closure, tapeout, and silicon correlation. Ideal for engineers who thrive on deep technical ownership.

Key Responsibilities:

- Architect and build scalable UVM testbenches from scratch (SoC/subsystem).

- Own TB architecture, reuse strategy, and maintainability.

- Define verification strategy and author test plans from specs and micro-architecture.

- Develop constrained-random & directed tests, scoreboards, checkers, SVA, and coverage models.

- Drive functional, code, and assertion coverage closure.

- Debug complex issues using waveforms, logs, and RCA.

- Lead SoC-level verification: IP integration, coherency, low-power, reset/boot, performance.

- Collaborate with RTL, architecture, DFT, and firmware teams.

- Support silicon bring-up and pre-/post-silicon correlation.

Mandatory Skills: ASIC Verification, SoC Verification, System Verilog, UVM, SVA, TB Architecture, Coverage Closure, AXI, DDR, PCIe