InnoPhase Inc., DBA GreenWave Radios Bangalore is looking for a Senior Engineer Design Verification to join our fast-paced and motivated team to drive excellence in our 5G products.

This role is an excellent opportunity for someone that enjoys driving the critical path and making a significant impact in launching products into the market and winning!.

Key Responsibilities :

- You will be working within DV team on verifying HW wireless DSP blocks using internal developed reference MATLAB/Python Model.

- Develop UVM testbench environment and execute verification cases to verify RTL design in bit true and cycle accurate.

- Construct SoC level testbench re-using verification components developed at the IP/ Subsystem level.

- Test bench architecture for random/directed testing, stimulus generation, and integration of custom and off the shelf VIP/UVCs.

- Develop and execute verification plans based on design specifications and collaboration with architects and designers.

- Construct HW/SW Co-Verification environment test-benches, use-cases, APIs, sequences.

- Execute and Debug use-cases.

- Be part of a dynamic and functionally diverse team with opportunities for gaining exposure to modelling (TLM), HW emulation/acceleration, and SW driven verification.

- Debug test cases and report verification result to achieve expected code/functional coverage metrics.

- Utilize constrained random verification, functional coverage, code coverage and assertions to achieve goals.

- Assist in emulation, FPGA, prototyping efforts.

- Implement and maintain automated verification flows in languages such as Python, Perl/ Shell scripts.

Job Requirements :

- Master's and/or bachelor's degree in engineering (or equivalent) in EC/ EE/ CS.

- 5 or more years of experience in DSP blocks(FFT, FIR, IIR, AGC, Interpolation/Decimation Filters, Up/Down Converter) design verification using reference models.

- Hands-on experiences in integrating MATLAB/Python models to UVM environment and create Agents, Scoreboards components for DSP blocks.

- Knowledge of wireless communication theories (SNR, IQ constellations, FFT, OFDM, MIMO).

- Experiences in Cadence vManager for DV metrics extraction and regression.

- Good understanding of the complete verification life cycle (test plan, testbench through coverage closure).

- Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc) from the scratch.

- Proficient in SystemVerilog, Verilog, UVM and C; and scripting languages like Python, Perl and Tcl/Shell.

- Experience in developing IP/ Subsystem/ chip-level SystemVerilog and UVM based.

- Experiences in GIT, JIRA, MS office suites.

Benefits :

- Competitive salary and stock options.

- Learning and development opportunities.

- Employer paid health Insurance.

- Earned, Casual, Sick & parental leaves.