Posted on: 05/08/2025
Job Overview :
The ideal candidate will have hands-on expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre.
This is a fantastic opportunity to work on cutting-edge analog and mixed-signal circuit layouts as part of a high-performance team.
Key Responsibilities :
- Collaborate closely with circuit design teams to interpret and implement layout specifications.
- Perform layout verification, including DRC, LVS, and parasitic extraction using industry-standard tools.
- Ensure compliance with foundry design rules and layout best practices for 5nm and below FinFET technologies.
- Address issues related to electromigration, IR drop (EMIR), and layout-dependent effects (LDE).
- Optimize layouts for performance, area, and reliability across PVT corners.
- Support tape-out and post-layout verification activities.
- Participate in design reviews and proactively resolve layout-related issues.
- Maintain proper documentation of layout guidelines, checklists, and review feedback.
Required Skills & Expertise :
- Strong working knowledge of FinFET nodes (6nm, 5nm or below) with exposure to leading foundries.
- Proficient in layout tools like Cadence Virtuoso, Calibre, and parasitic extraction tools.
- Sound knowledge of DRC, LVS, and EMIR verification methodologies.
- Understanding of layout effects such as matching, shielding, symmetry, and noise isolation.
- Familiarity with EDA scripting (Skill, Tcl, Python) is a plus.
- Strong problem-solving skills and attention to detail.
- Good communication and collaboration abilities in a team-based environment.
Why Join Us?
- Join a fast-growing semiconductor team working on impactful silicon designs.
- Competitive compensation and career development opportunities
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Posted By
Posted in
Semiconductor/VLSI/EDA
Functional Area
Embedded / Kernel Development
Job Code
1524929
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