Ignitarium - Principal Engineer - Physical Design

Company Description :

Ignitarium is a Silicon and Embedded System design house focused on delivering innovative, optimal, and relevant solutions for product development. Built around a core team of technologists with over 150 years of collective industry experience, Ignitarium specializes in system architecture, logic design and verification, signal processing, FPGA design, and embedded system design along with associated software development. Our aim is to assist our customers in bringing their product visions to life.

Role Description :

Qualifications :

- Should have worked on the latest technology nodes (14nm or lesser).

- Must have experience in Static timing analysis.

- Must have experience in Physical verification and appropriate fixes.

- Should have worked on block level and top-level designs.

- Good to have worked on designs without a customer flow.

- Strong problem-solving skills and communication skills.

- Ability to mentor and work closely with junior engineers.

- Minimum of 14 years of industry experience in relevant domains.

Key Skills :

Verification & Analysis: Static Timing Analysis (STA), Design Rule Check (DRC), Layout Versus Schematic (LVS).

Technology Node Experience: Hands-on experience with advanced nodes (14nm or smaller; FinFET experience preferred).

Physical Verification: Experience in debugging and implementing appropriate fixes.

Design Levels: Worked on both block-level and top-level designs.

Customer Flow Independence: Experience handling designs without relying on customer-specific flows (preferred).

Strong problem-solving and analytical abilities.

Excellent communication and collaboration skills.

Ability to mentor and guide junior engineers.

Proven track record in delivering complex projects within tight timelines.

Responsibilities :

- Develop and implement efficient system architecture for optimal performance.

- Execute and oversee logic design and signal processing optimization.

- Perform timing closure, power optimization, and physical verification (DRC, LVS).

- Manage block-level and top-level integration, ensuring consistency and quality.

- Ensure designs meet PPA (Power, Performance, Area) targets and sign-off requirements.

- Act as a technical authority in physical design methodologies and best practices.

- Collaborate with cross-functional teams, including architecture, RTL design, verification, and package engineering.

- Mentor junior engineers, providing guidance on problem-solving and design techniques.

- Contribute to process improvements and adoption of new tools/flows.

- Monitor project schedules, risks, and deliverables to ensure on-time completion.

- Minimum 14 years of relevant experience in VLSI physical design.

- Proven expertise in advanced technology nodes (14nm or below).

- In-depth experience with EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, etc.

- Demonstrated success in leading complex design projects from concept to tape-out.