Description : DFT Lead - 8+ Years Experience

Location : Bangalore

Job Overview :

We are seeking an experienced Design-for-Test (DFT) Lead with strong expertise in DFT architectures and implementation to drive test strategy and execution for complex ASIC/SoC designs. The ideal candidate will have hands-on experience across the complete DFT flow, deep understanding of scan-based testing techniques, and proven leadership in owning DFT deliverables from architecture to signoff.

This role requires close collaboration with design, physical design, and test teams to ensure high test coverage, quality, and manufacturability.

Key Responsibilities :

- Own and drive DFT architecture definition and implementation for IPs and SoCs

- Architect and implement DFT features including :

1. JTAG / IEEE 1149.x

2. Scan chains and scan compression

3. Boundary scan

- Lead the complete DFT flow including planning, insertion, verification, and signoff

- Implement and validate scan compression techniques to optimize test time and coverage

- Ensure high fault coverage and quality metrics (stuck-at, transition, path delay, etc.)

- Perform DFT rule checks and debug DFT-related issues at RTL and gate levels

- Collaborate with Physical Design teams to resolve scan-related implementation issues

- Work with validation and manufacturing test teams to support test pattern generation and silicon bring-up

- Review and sign off DFT deliverables, documentation, and tapeout readiness

- Mentor junior engineers and provide technical leadership within the DFT team

Required Skills & Experience :

- 8+ years of hands-on experience in DFT design and implementation

- Strong understanding of DFT architectures, including :

1. JTAG / boundary scan

2. Scan chains and scan-based testing methodologies

- In-depth experience with Scan Compression techniques

- Extensive hands-on experience with Synopsys DFT tools (mandatory) :

1. DFT Compiler

2. TestMAX / ATPG (or equivalent)

- Solid understanding of ASIC/SoC design flows and interaction with synthesis and physical design

- Proven ability to debug complex DFT and scan-related issues

- Ability to independently own DFT execution for blocks or full-chip designs

Preferred / Nice-to-Have Skills :

- Experience with low-power DFT features

- Exposure to at-speed testing and advanced fault models

- Familiarity with post-silicon debug and manufacturing test flows

- Experience acting as a technical lead or DFT signoff owner

- Excellent communication and cross-functional collaboration skills

Location : Bangalore