DFT Architect

Description :

Company Description :

Chiplogic Technologies (Chiplogic), established in 2018, is a trusted provider of IP and Product Engineering Services, delivering high-quality solutions across Semiconductor, Systems, IoT, and AI/ML domains. The company specializes in offering comprehensive services, including ODC, turnkey semiconductor design, system solutions from concept to silicon, as well as IoT solutions and AI/ML services. Chiplogic leverages its proprietary VISARD (Video Synthesis and Real-time Dynamics) framework for creating innovative solutions that meet client needs.

Role Description :

This is a full-time, on-site role for a DFT Architect, located in Bengaluru. The DFT Architect will be responsible for designing and developing chip architectures, implementing software and integration plans, and providing efficient architectural designs. The role also involves collaborating with teams for project planning, management, and successful execution to meet project goals and deadlines.

Qualifications :

- Proficiency in Architecture and Architectural Design

- The candidate should have 7+ years of experience in DFT

- Experience in Software Development and Integration processes

- Strong skills in Project Management and the ability to oversee and execute technical projects

- Analytical mindset with problem-solving skills and attention to detail

- Bachelors or Masters degree in Engineering (Electronics, Electrical, or related field)

- Prior experience in chip design or semiconductor industries is highly advantageous

- Prior 7+ years of professional experience in SoC/ASIC Digital Design with focus on Design for Test (DFT)

- Should possess intimate knowledge of DFT insertion flows

- Basic scan chain insertion using synthesis or other software tools

- Experience in compression scan insertion, LBIST and other scan technologies

- Intimate knowledge of memory build-in self-test (MBIST)

- Expertise in Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals

- Debug and Analysis of failures to improve fault coverage

- Verification of ATPG testbenches and debugging root cause of simulation mis-compares

- Working knowledge of JTAG 1149.1/6, IEEE1500 and IEEE1687

- Knowledge of timing analysis and equivalency checks would be added bonus

- Ability to work in collaborative team environment

- Prior experience with Cadence tools and flows is highly desirable

- Should be able to finish DFT tasks independently