- Develop and execute verification plans at IP, subsystem, and SoC levels

- Build SystemVerilog/UVM test-benches with monitors, checkers, and coverage metrics

- Perform RTL, gate-level, low-power simulations; ensure ISO 26262 compliance

- Identify and resolve functional and safety bugs across hardware/software interfaces

- Support post-silicon validation and customer issue resolution

- Drive automation using Python, Perl, or Shell scripting

What We're Looking For :

- Proficiency in System Verilog, UVM, and verification toolchains (Cadence, Synopsys, Mentor)

- Understanding of automotive protocols (MIPI, CAN, Ethernet, SPI) and safety mechanisms

- Exposure to ARM/RISC-V architectures, CDC, and power-aware verification

- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field

Nice-to-Haves :

- Experience with ASIL-level safety verification, fault injection, and coverage-driven methodology

- Familiarity with firmware interaction debugging and hardware/software co-verification

- Hands-on with post-silicon bring-up and regression automation