Mandate Required Skillset :

- RTL Verification Experience: 7 years of hands-on experience verifying RTL designs for digital systems or SoCs.

- Simulation Tools Proficiency: Expertise in using industry-standard verification tools such as ModelSim, Cadence Incisive, and Synopsys VCS.

- Testbench Development: Proficient at developing and maintaining verification environments and testbenches using SystemVerilog, UVM, Verilog, or VHDL.

- Functional Verification: Strong background in functional verification, writing test plans, creating test cases, debugging failures, and ensuring design quality.

- Scripting for Automation: Experience scripting with Python, Perl, or TCL to automate verification workflows and enhance productivity.

- Coverage Analysis: Familiar with coverage-driven verification methodologies (functional and code coverage).

- Team Collaboration: Excellent communication and teamwork skills for efficient interaction with design and architecture teams.

- Problem Solving: Strong analytical skills to identify, debug, and resolve complex design and verification issues.

Nice To Have :

- Experience with formal verification tools.

- Exposure to FPGA prototyping and hardware emulation.

- Knowledge of industry standard protocols (e.g., AXI, PCIe, USB).