Design Verification Engineers for one of our clients at Bangalore location.

Experience : 7+

Notice Period : Immediate 30 days.

5 Days work from office.

Role and Responsibilities :

- He/she will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores.

- Candidate will work closely with Verification lead and be part of a global team of experienced Verification Engineers.

- Job role will have a combination of Test planning, Test environment coding both at IP level, Test case coding and debugging, FC coding and review and meeting quality metric goals and regression management.

Key Qualification :

- BS/MS in EE/EC with 5+ years of relevant experience in the verification of IP cores.

- Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage.

- Experience on DDR Protocol is necessary.

- Understanding of BIST would be an added advantage.

- Familiarity with HDLs such as Verilog and scripting languages such as shell/Perl/Python etc. is highly desirable.

- Good communication skills, debug and problem-solving skills, mentoring teammate and should be self-motivated.

Preferred Experience :

- Be a technical contributor in the Verification Tasks System Verilog/Verilog coding of testbenches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM.

- Creates deliverables which do not require close review or supervision by a Senior Technical Engineer.

- Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/medium complexity features of the protocol/ product specs.

- Works in a project and team-oriented environment with teams spread across multiple sites, worldwide.