Cadence Design Systems - Lead Product Engineer - Static Timing Analysis

Role Overview :

As a Lead Product Engineer, you will play a key technical role in defining, driving, and deploying cutting-edge features and solutions in the domain of Static Timing Analysis (STA) using Cadences flagship Tempus Timing Signoff platform. You will collaborate closely with R&D, customers, and field engineering teams to advance signoff-level accuracy and performance across real-world SoC designs.

Key Responsibilities :

Advanced STA Deployment :

- Drive adoption and support of Cadence's Tempus tool in advanced timing closure and signoff flows.

- Perform comprehensive STA using SDC constraints, PBA/GBA methodologies, and advanced

ECO flows.

Design Enablement & Ecosystem Integration :

- Define and enable use cases that integrate Tempus with synthesis, place & route, IR drop, and EM analysis flows.

- Collaborate with design teams to ensure end-to-end timing convergence at advanced nodes (5nm, 3nm, and below).

Feature Specification & Roadmap Contribution :

- Gather and analyze customer requirements and translate them into robust, production-ready product specifications.

- Propose enhancements and new feature ideas to improve timing analysis accuracy, runtime, and usability.

Debug & Validation Expertise :

- Reproduce and debug complex timing scenarios including OCV, CRPR, path-based analysis, and clock-domain crossings.

- Develop validation flows for STA features using industry benchmarks and regression infrastructure.

Cross-functional Collaboration :

- Work closely with R&D, application engineers, and field AEs to validate new capabilities and improve customer satisfaction.

- Provide technical training, best practices, and documentation to internal teams and end users.

Required Skills & Experience :

- Strong background in digital design and static timing analysis.

- Expertise in EDA tool usage, specifically Tempus, PrimeTime, or similar STA tools.

Deep understanding of :

- Timing constraints (SDC), clock tree synthesis, ECO closure

- Multi-mode multi-corner (MMMC) analysis

- On-chip variation (AOCV/POCV), derating, and margin analysis

- Proficiency in TCL, Python, and scripting for tool automation and debugging.

- Familiarity with RTL-GDSII design flow, synthesis, PnR, and DRC/LVS signoff.

- Experience working with advanced process nodes (FinFET/GAA) is a strong plus.

- Excellent communication, problem-solving, and cross-functional collaboration skills.

Educational Qualification :

- B.Tech/M.Tech in Computer Engineering from a reputed institute.