APPEX - Design Verification Engineer - System Verilog

Job Title : Senior Design Verification Engineer (DV)

Location : Bangalore

Experience : 5+ Years

Notice Period : 15 to 30 Days

Job Description :

We are looking for a Design Verification Engineer with strong experience in SystemVerilog and UVM for IP/SoC verification.

Key Skills Required :

- Strong in System Verilog (SV) and UVM

- Experience in Functional Coverage & Code Coverage

- Knowledge of System Verilog Assertions (SVA)

- Strong in Constrained Random Verification

Protocols :

Good to Have :