Desired Profile : - B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering. - Expertise in ASIC / SOC verification. - Expertise in UVM, System Verilog and constrained random testing. - Expertise in testbench architecture and SOC-level verification strategies. - Expertise with protocols such as AXI, AHB, APB, PCIe, USB, or DDR. - Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa. - Familiar with waveform debugging tools such as Verdi or DVE. - Working knowledge of low-power verification (UPF) and DFT / scan concepts. - Knowledge of scripting languages (Python, Perl, TCL) for automation. - Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Job Specs : - Develop and maintain full-chip verification environments using System Verilog UVM methodology. - Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE). - Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features. - Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level. - Perform debugging, waveform analysis, and triage of failures in RTL simulations. - Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied. - Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues. - Participate in formal verification, assertion-based verification, and low-power simulations. - Support regression testing, issue tracking, and coverage closure. VISA SPONSORED FOR IMMEDIATE HIRES

Singapore

ASIC SoC Verification Engineer (5-13 yrs)

Job Description : - Expertise in the verification of IP or SOC cores. - Must have proven experience in developing HVL (System Verilog/UVM) based test environments, developing and implementing test plans, implementing and extracting verification metrics such as functional coverage and Code coverage. - Experience in CXL / DDR / MIPI / PCIe Protocol - Understanding of BIST would be an added advantage. - Familiarity with HDL's such as Verilog and scripting languages such as shell/Perl/Python etc.is highly desirable - Good communication skills, debug and problem solving skills. - Be a technical contributor in the Verification Tasks - System Verilog/Verilog coding of test benches, Test cases, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM. - Work closely with team members to deliver quality products. - Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs - Works in a project and team oriented environment - Preferred GCC / USC or candidates with valid H1B

Overseas/International

Others

Digital Verification Engineer - UVM/System Verilog (5-15 yrs)

Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 5 - 15 years Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

Bangalore

BIOS Development Engineer - Hardware Architecture (5-15 yrs)

Job Specs : We are seeking a highly skilled and motivated Firmware Software Development Engineer (Memory Management) to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of embedded products. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 3 - 8 years Desired Profile : - Engineers with expertise in firmware development related to memory recognition and configuration code - Expertise in embedded C programming - Expertise in using hardware debug tools - Good problem solving, analysis and debugging skills - Good understanding of DDR4, DDR5, NVDIMM - Good understanding of different DIMM types (UDIMM / SODIMM / RDIMM / LRDIMM / LPDDR) - Good understanding of UMC features like ECC, SME, SEV, RAS etc - Understanding of different vendor implementations and memory timing difference is a big plus - Knowledge of platform BIOS and UEFI / Coreboot is a big plus - Scripting knowledge is a plus Rewards and Benefits : We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. NOTE : Preferred resources holding valid regional work permits only

Firmware Development Engineer - Memory Management (3-8 yrs)

Desired Profile : You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. Academic Credentials : MS or BS in Computer Engineering/ Computer Science with 5+ years working experience in ASIC RTL design. Key Responsibilities : 1. Develop micro-architecture and design for high-speed IO controller blocks based on architectural requirement 2. Conduct design reviews of designs in technical presentations to peers and management. 3. Develop RTL code for high-speed IO controller blocks in Verilog HDL and make sure functional correct and reusable for different configuration. 4. Oversees Synthesis and netlist delivery that meets timing, area and power bounding box. Assist physical design team on the floor-planning and timing closure. 5. Work with Design Verification team to ensure quality for architecture definition and design implementation. 6. Provide guidance and leadership to the team members. Preferred Experience : 1. Strong knowledge in computer architecture and interconnects. 2. Strong experience in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt). USB and/or Thunderbolt a strong plus. 3. Experience in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation. 4. Expert on Verilog RTL design and has experience of large digital ASIC project. 5. Familiar with front-end EDA tools and flows. 6. Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.) 7. Preferred candidates with valid work permit (Green Card / US Citizen / H1B)

RTL Design Engineer (5-15 yrs)

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