At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Analog Design (7-14 years of exp). Education : BE/BTECH/ME/METCH or Equivalent Degree. BE/ B Tech/ ME/ M Tech / MS. Job Role : - In-depth understanding of high-speed Serdes/Memory interface circuits like I/Os,PLLs, Clocking, Datapaths. - Hands on experience on PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits. - Must have exposure : High speed analog circuit design, Exposure to high-speed Tx-Rx designs, Preferable to have exposure to high speed Phy architecture. - Must have exposure : High speed analog circuit design, Exposure to Architecture understanding of multiple high-speed analog Phy PCIe, DDR, including Die-die protocols etc. - Strong Analog Design and I/O Design fundamentals. - Knowledge of ESD/Reliability/SI/PI. - Experience in leading complex IPs , managing cross functional dependencies needed. - Experience in leading and mentoring Junior Engineers. - Must have excellent written and verbal communication skills as well as good problem-solving skills. - Prior experience of working on cutting edge technology nodes like 16nm/10nm/12nm/7nm is added advantage.

Others

Cadence Design Systems - Principal Design Engineer - Analog/Circuit Design (7-14 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage. The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day. Summary: Lead Software Engineer plays a critical role in the development and maintenance of software applications. They are responsible for designing, coding, testing, and debugging programs, as well as collaborating with teams to ensure project success. This role typically involves the following responsibilities:. Qualifications : BE/BTech/ME/MS/MTech in computer Science. Job Summary : Exp : 2+yrs. - Excellent knowledge of C/C++ (C++11 and C++14 knowledge is added advantage). - 2-3+years of experience on design and development of complex software projects. - Strong background on Data Structures, Algorithms, and Design Patterns. - Excellent problem solving and debugging skills. - Willingness to explore new technology areas, formulate problem statements and independently work on solutions. - Familiarity with Qt (Quick Time). - Knowledge and experience with EDA flows and applications would be a significant plus.

Cadence Design Systems - Software Engineer II - C++11/C++14 (2-5 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Principal Software Engineer (Development and verification of VIP). Location: Bangalore / Ahmedabad. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage. The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary. We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. As part of this highly talented team, the candidate will develop, implement, and test features for the next generation of verification IP tools. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each others success, and are passionate about technology and innovation. Job Responsibilities. Responsible for the development and verification of VIP. Experience And Technical Skills Required. - 8 + years or relevant years of domain experience. - Proficiency in functional verification using SV/UVM and strong debugging skills. - Hands-on knowledge of Python/Scripting. - Working experience on memories like HBM, LPDDRR, GDDR and DDR. - (HBM, GDDR knowledge is plus). - Prior VIP usage and development experience is a plus. - Strong Digital Electronics and Programming fundamentals. - Self-motivated individuals with strong analytical and communication skills. Behavioral Skills Required : - Must possess strong written, verbal and presentation skills. - Ability to establish a close working relationship with both customer peers and management. - Explore whats possible to get the job done, including creative use of unconventional solutions. - Work effectively across functions and geographies. - Push to raise the bar while always operating with integrity.

Bangalore

Ahmedabad

Cadence Design Systems - Principal Software Engineer - Development & Verification (8-10 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage. The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary : We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each others success, and are passionate about technology and innovation. Job Responsibilities : Experience : 5+yrs. - Strong CS fundamentals background in data structures, algorithms, systems architecture and/or databases. - Expert in C++, gdb debugging, and general software development skills. - Improve QoR of protium P&R tool. - Implement feature to improve P&R time for Protium P&R component. - Work with user to deploy new features/tools.

Cadence Design Systems - Lead Software Engineer - System Architecture (5-8 yrs)

About Cadence : Cadence is a global leader in computational software, enabling electronic systems and semiconductor companies to create innovative end-products. With cutting-edge tools and platforms, Cadence accelerates innovation in the most advanced IC and system designs. Join a team that's transforming the design industry through intelligent system design and impactful solutions. Role Overview : As a Senior Application Engineer (AE2) in the Custom IC (CIC) Frontend domain, you will be responsible for driving successful engagements with semiconductor and systems companies by enabling the deployment of Cadences analog/mixed-signal design and simulation technologies. This role requires a deep technical understanding of analog and mixed-signal IC design flows, a customer-focused mindset, and a hands-on approach to problem-solving and tool deployment. Key Responsibilities : - Engage directly with customers and prospects to understand design methodology, identify challenges, and map requirements to Cadence solutions. - Define and drive successful product evaluations and proof-of-concepts based on achievable metrics aligned with customer success criteria. - Support pre-sales and post-sales activities including product demonstrations, benchmarking, and tool deployment. - Collaborate with internal R&D, product engineering, and field engineering teams to address tool limitations, suggest enhancements, and resolve customer issues effectively. - Drive methodology adoption and best practices to improve productivity and simulation accuracy in customer design environments. - Analyze complex analog/mixed-signal design challenges and provide solutions leveraging Cadence tools like Virtuoso, Spectre, AMS Designer, etc. - Deliver technical training, documentation, and support collateral tailored to customer needs. Required Technical Skills : - Proficient in analog and mixed-signal design methodologies. - Hands-on experience with Virtuoso Schematic Editor, Virtuoso ADE, Spectre, Spectre X, and AMS Designer. - Strong understanding of analog front-end design flow including : 1. Design entry and schematic capture 2. Behavioral/real number modeling (SystemVerilog, Verilog-AMS) 3. Pre-layout and post-layout simulation 4. Mixed-signal co-simulation environments 5. EM/IR and power integrity analysis - Familiarity with advanced simulation techniques including noise analysis, Monte Carlo, corner analysis, and parametric sweeps. - Good scripting ability in SKILL, Python, Shell, or TCL to automate tasks and improve flows. Preferred Qualifications : - Prior exposure to customer-facing roles in EDA or semiconductor environments. - Experience in circuit debugging, modeling, and root cause analysis in simulation environments. - Understanding of foundry PDK integration and device modeling. - Ability to interpret and work with industry-standard models (e.g., BSIM, PSP). - Exposure to verification planning and regression setup for analog designs.

Cadence Design Systems - Senior Application Engineer (4-8 yrs)

At Cadence : At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title : Software Engineer II Location : Noida Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage : The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day. Job Summary : We are seeking a highly motivated candidate with expertise in functional verification, specifically focusing on Verification IP (VIP) development. The ideal candidate will be able to quickly and independently adapt to new technologies and protocols. Excellent communication skills are essential, as the role involves cross-functional collaboration and close interaction with customers. Job Responsibilities : - Responsible for the design, development, verification and deployment of the VIP. Experience And Technical Skills Required : - 2 to 5 years of domain experience. - Proficiency in functional verification, test environment creation using SV/UVM with strong debug skills. - Hands-on knowledge of C/C++/Scripting. - Working experience on layered Protocols UCIe, PCIe, CXL, Ethernet. - Prior VIP usage and development experience is a plus. - Strong Digital Electronics and Programming fundamentals. - Self-motivated individuals with strong analytical and communication skills. Qualifications : - BE/BTech/ME/MS/MTech Behavioral Skills Required : - Demonstrate adaptability in a fast-paced environment, showing resilience in the face of challenges and maintaining a positive attitude. - Exhibit a strong commitment to continuous learning and professional development, staying abreast of industry trends and technologies. - Foster a collaborative team environment by being approachable and supportive. - Display a proactive approach to problem-solving, taking initiative, and anticipating potential issues before they arise.Were doing work that matters. Help us solve what others cant.

Noida

Cadence Design Systems - Software Engineer II - Functional Verification (2-5 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.. The Cadence Advantage. The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day. Position : IT -Sr Systems Engineer Grade : IT3 Location : Noida/Bangalore, India Job Description : - Provide Windows system administration & support. - Perform windows and Linux installation, upgrades, customization, recovery, and performance tuning. - Support laptops, desktops and desktop application issues like Microsoft Office/adobe application, VPN, Emulations client software NX/VNC/ETX reported by end-users. - Support O365 services Email clients, Intune, Teams, OneDrive. - Work on Windows security compliance and remediation. - Troubleshoot any issues with infrastructure services like Active Directory, DNS, DHCP, File/Print services. - Work on Windows Infrastructure upgrade/improvement projects/tasks. - Support end users remotely from WW sites. - Perform other duties as assigned. Requirements : - Technical knowledge of the fundamental concepts and technologies associated with Windows Operating System. - Should have very good skills in Windows administration & Scripting (PowerShell, Python, - Should have good knowledge of Microsoft OS version Windows 10/11, Windows server 2016/2019/2022. - Should have knowledge of Infrastructure services Active Directory, DNS, DHCP, Group Policies. - Should have working experience on O365 technologies. - Strong analytical/problem solving and troubleshooting skills. - Good written and verbal Communications Skills. Experience : - Should possess at least 6-8 yrs. of relevant IT system administration experience. - Prior experience of providing onsite and remote end user support. Qualification : - Engineering (Computers/ IT) Were doing work that matters. Help us solve what others cant.

Cadence Design Systems - Senior Systems Engineer - Windows Administration & Support (2-6 yrs)

Company Overview : At Cadence Design Systems, we develop cutting-edge software that enables the design and optimization of next-generation semiconductors and electronic systems. Our Intelligent System Design strategy drives innovations in computational software, enabling digital design engineers to deliver scalable, automated, and high-performance solutions for complex SoCs and electronic systems. Role Overview : We are seeking a Software Engineer I with a strong foundation in data structures, algorithms, and software development to contribute to the creation and enhancement of our EDA (Electronic Design Automation) tools. In this role, you will build high-performance software components that power the RTL-to-GDSII implementation flow, focusing entirely on the software stackcore engines, optimization algorithms, ML integration, and customer enablement scripts. Key Responsibilities : EDA Software Development : - Contribute to the design and development of core algorithms and software modules that drive Cadences digital design tools (e.g., synthesis, placement, routing, timing optimization). Flow Automation & Customization : - Build robust scripting and automation layers (TCL/Python) to enhance user productivity and customize workflows for various customer use cases. Performance Optimization : - Profile and optimize existing software components to improve execution speed, scalability, and memory footprint across real-world designs. Machine Learning Integration : - Develop and deploy ML-driven models to enhance tool behavior in areas such as congestion prediction, timing closure assistance, or routing heuristics. Problem Solving & Debugging : - Analyze complex software behavior, debug runtime issues, and work with cross-functional teams to ensure high-quality product delivery. Customer-Centric Solutions : - Collaborate with application engineers and customer teams to implement and refine tool features based on real design requirements. Agile Collaboration : - Participate in agile development cycles, including code reviews, sprint planning, and continuous integration testing. Required Skills & Qualifications : - B.E./B.Tech or M.E./M.Tech in Computer Science, Software Engineering, or a related field. - Strong programming skills in C++ and/or Python. - Solid understanding of data structures, algorithms, and software design principles. - Familiarity with EDA tools, digital design flows, or compiler/optimization software. - Experience with scripting languages (TCL, Perl, or Python) for automation and workflow development. - Exposure to version control systems (Git), debugging tools, and unit testing frameworks. - Strong analytical and debugging abilities; able to work through complex software problems independently.

Cadence Design Systems - Software Engineer I (7-10 yrs)

About Cadence : Cadence Design Systems is a global leader in computational software for electronic design automation (EDA). Our Intelligent System Design strategy powers innovation in electronic products, delivering software-driven solutions that help build next-generation systems across AI, automotive, 5G, hyperscale, consumer, and industrial applications. As a part of Cadence, Invecas drives innovation in system-level software design and optimization. Role Overview : As a Software Engineer 1, you will play a pivotal role in designing and developing scalable, modular, and reusable software solutions for chiplet and subsystem platforms. This includes embedded software components, drivers, system software, and tooling that support the full software stack from the lowest levels to the application interface. You will be engaged in architecture, design, implementation, testing, and optimization of software that supports advanced SoC features and cross-chiplet interoperability. This role offers an opportunity to shape the direction of Cadence's software ecosystem for chiplet-based designs and to work closely with multidisciplinary teams across the organization. Key Responsibilities : - Design and implement embedded and system-level software for chiplet-based subsystems. - Develop drivers, board support packages (BSPs), and firmware for various IP and SoC configurations. - Create software that is highly configurable, reusable, and automated for various product variants. - Collaborate with architecture teams to define the software abstraction layer and interfaces. - Define and implement robust software development processes including version control, static analysis, code reviews, CI/CD integration, and test automation. - Debug and troubleshoot complex software issues, both independently and in collaboration with internal teams. - Review technical documentation, system designs, and contribute to technical decision-making. - Participate in architectural reviews, software planning, and requirement discussions. Technical Skills & Experience : - 2- 5 years of hands-on experience in embedded systems or system-level software development. - Proficient in C/C++ programming with strong software engineering fundamentals. - Solid understanding and practical experience in : 1. RTOSes (e.g., FreeRTOS, Zephyr, VxWorks) or embedded Linux systems. 2. Device driver development, especially for I/O peripherals. 3. Firmware and BSP development for multi-core SoCs. - Software boot sequences, initialization flows, and interrupt handling. - Good understanding of software constructs in multi-threaded/multi-core systems. - Familiarity with software interfaces and protocols such as SPI, I2C, I2S, USB, PCIe, MIPI, etc. - Knowledge of processor architectures such as ARM Cortex-A/M or RISC-V is an advantage. - Exposure to software simulation, emulation, or pre-silicon development environments is a plus. - Experience in scripting languages (Python, Bash) for automation and toolchain orchestration is desirable. Preferred Qualifications : - Bachelor's or Masters degree in Computer Science, or a related field. - Experience working in agile or iterative software development methodologies. - Familiarity with version control systems (e.g., Git), bug tracking tools, and CI pipelines. - Exposure to software security, code quality metrics, and release management is beneficial. Behavioral Competencies : - Strong analytical and problem-solving skills with a detail-oriented mindset. - Excellent verbal and written communication skills. - A collaborative approach to working with cross-functional teams. - Self-driven with a high level of ownership and accountability. - Ability to learn and adapt quickly to evolving technologies and customer requirements.

Hyderabad

Cadence Design Systems - Software Engineer I - Embedded System (2-5 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Seeking an experience IT project manager with a working knowledge of IT infrastructure to successfully manage global IT projects from initiation to delivery. Role includes effectively managing scope, timeline, risks, and success criteria of medium-to-large, cross-functional projects. Key Responsibilities Include : - Driving and maintaining vital project assets (like comprehensive project plans, status reporting, communication plan, and risk register) to ensure successful project delivery. - Partnering with the Project Owner to address blockers. - Anticipating critical risks and coordinating teams to appropriately remediate. - Effectively and consistently communicating project status, dependencies, and risks to stakeholders, the team, the PMO, and IT Leadership. Qualifications : - 5 -7 years of project management experience. - Experience with IT infrastructure, application, security, and M&A projects. - PMP certification or equivalent preferred. - Demonstrable knowledge in project management software, including Smartsheet and Jira Software. - Strong communication, facilitation, and influence skills. - Ability to build strong and collaborative relationships with individuals at all levels. - Dynamic and open to new approaches or change. - Bachelors degree in business, computer science, or related field. - Were doing work that matters. - Help us solve what others cant.

Cadence Design Systems - IT Project Manager (5-7 yrs)

About the Role : We are seeking highly skilled and motivated DFT Engineers to join our dynamic semiconductor design team. The ideal candidate will have extensive experience in SCAN/ATPG/JTAG/MBIST implementation and verification, along with hands-on involvement in multiple chip tape-outs and post-silicon bring-up on ATE platforms. You will be an integral part of the silicon development lifecycle, contributing to DFT architecture, verification, and debug. Key Responsibilities : - Develop and implement SCAN, ATPG, JTAG, and MBIST architectures at block and top level. - Execute scan insertion and DFT rule checking at RTL/Netlist level. - Work on Memory BIST generation, insertion, and functional verification. - Perform gate-level simulations (GLS) with and without timing (SDF). - Develop and integrate test structures for DFT, including IP integration, fault modeling, test point insertion, and coverage optimization. - Collaborate with cross-functional teams (Design, Synthesis, STA, and PD) to resolve DFT integration issues. - Work on IEEE standard JTAG architectures (1149.1 / 1149.6) and related scan chain verification. - Define and validate test mode timing constraints and participate in STA signoff. - Support silicon bring-up and debugging on ATE platforms, ensuring high-quality silicon validation. - Utilize industry-standard tools (Cadence, Synopsys, Siemens Tessent) for ATPG, MBIST, and boundary scan implementation. - Create and maintain DFT scripts using Perl, Tcl, or similar scripting languages. Required Skills & Qualifications : - Bachelor's or Master's degree in Electronics, Electrical, or related Engineering fields. - 10 - 14 years of relevant experience in DFT implementation and validation. - Strong understanding of digital design principles, scan logic, and fault models. - Hands-on experience with scan/ATPG tools (preferably Tessent or Cadence). - Proficient in GLS with and without timing (SDF). - Knowledge of Analog PHY/Macro test concepts and integration. - Solid understanding of JTAG and IEEE standards (1149.x). - Proficiency in Perl/Tcl scripting for automation of DFT flows. - Proven experience in resolving DFT issues through collaboration with multi-disciplinary teams. - Strong verbal and written communication skills. - Ability to take ownership and work independently in a fast-paced environment. Preferred : - Experience with multiple successful chip tape-outs and post-silicon validation. - Familiarity with STA and timing closure for test modes.

Cadence Design Systems - DFT Engineer - Embedded System (10-14 yrs)

About the Role : Cadence Design Systems is seeking a technically driven and highly collaborative Functional Safety Engineer to join our Silicon Solutions Group (SSG). In this role, you will spearhead the definition, execution, and certification of safety processes compliant with ISO 26262 and ISO 21434 for our automotive-grade IP, including processors, hardware accelerators, and controllers. This role is crucial in driving safety architecture, process development, and safety case delivery for our advanced semiconductor IP portfolio targeting ADAS, autonomous driving, and automotive SoCs. You will directly interface with internal development teams, customers, third-party safety consultants, and ecosystem partners to deliver robust functional safety solutions aligned with evolving automotive standards. Key Responsibilities : Safety Lifecycle Execution : - Lead and coordinate the implementation of ISO 26262 safety lifecycle across product development phases for IP classified as SEooC (Safety Element out of Context). Safety Work Product Development : Author and maintain ISO 26262-compliant artifacts including : - Safety Plan - Safety Manual - Safety Requirements Specification - Safety Case - FMEDA, DFA, FMEA, and FTA analyses - Safety Verification & Validation strategies Cross-functional Collaboration : - Work closely with RTL, DV, architecture, synthesis, and product marketing teams to embed safety requirements into the design process. - Provide safety guidance throughout IP development including synthesis and verification flows. Safety Architecture Definition : - Participate in and influence the design of safety mechanisms, diagnostic coverage, redundancy, and fail-operational capabilities for various IPs. Process & Compliance : - Drive the creation, optimization, and automation of functional safety processes, ensuring alignment with ISO 26262, ASPICE, and ISO 21434. - Support audits and assessments to achieve and maintain functional safety certifications. Customer and Partner Engagement : - Act as a technical representative in discussions with automotive OEMs, Tier-1s, and external safety assessors to present safety strategies and justify compliance. Required Qualifications : - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. - 5+ years of hands-on experience in digital IP/SoC design, verification, or functional safety. - Solid understanding of IP development processes (RTL, verification, synthesis, integration). - Demonstrated experience with microprocessors, DSPs, or hardware accelerators. - Strong documentation, analytical, and debugging skills. - Proven experience in authoring technical documentation for safety deliverables. - Familiarity with EDA tools and flows (Synopsys, Cadence, Siemens). Preferred Skills : - Deep understanding of ISO 26262 functional safety standard and its implementation in IP or SoC context. - Working knowledge of FMEDA, FMEA, FTA, and safety goal decomposition. - Practical exposure to fault injection, diagnostic coverage analysis, and safety mechanism verification. - Experience with embedded hardware/software systems, especially in automotive applications. - Proficiency in scripting and automation (Python, Perl, Tcl). - Familiarity with configuration, requirements, and defect tracking tools (e.g., Jama, JIRA, Perforce). - Understanding of ISO 21434 (Automotive Cybersecurity). - Exposure to ISO 9001, ASPICE, or other process maturity models is a plus. Working Conditions & Travel : - Occasional domestic and international travel for customer interactions, audits, and conferences. - Flexible working hours with global team collaboration.

Pune

Cadence Design Systems - Functional Safety Engineer (5-8 yrs)

About Cadence : Cadence is a global leader in electronic design automation, known for driving innovation across semiconductors, systems, and AI-driven computing platforms. With over three decades of computational software expertise, Cadence delivers advanced technologies that enable our customers to build extraordinary electronic products. Role Overview : We are seeking a highly motivated and technically strong Lead Analog Design Engineer to drive the design and development of high-speed PHY IPs such as USB3, PCIe, DPHY, and more. You will be a key contributor in the analog design domain and participate in the full lifecycle of IP developmentfrom specification to silicon validation. This role also involves collaboration with layout, digital, and system-level teams, along with customer-facing engagements. Key Responsibilities : - Lead and contribute to the design of high-speed analog/mixed-signal IPs including PLLs, data converters, and high-speed serial interfaces (USB3, PCIe, MIPI DPHY, etc.) - Own and execute full custom analog design including transistor-level schematic design, simulation, verification, and silicon debug - Collaborate closely with layout engineers to ensure optimal layout and performance of the analog blocks - Support physical design and post-layout validation, ensuring compliance with power, performance, and area (PPA) targets - Perform integration of analog IPs into larger SoC environments and validate at chip level - Participate in silicon characterization, debug, and bring-up on ATE or lab platforms - Document design specifications, simulation results, test plans, and silicon results - Interface with cross-functional teams including digital, software, validation, and application engineers to deliver robust and production-quality IPs - Engage in technical discussions with customers to understand requirements, support integration, and resolve post-silicon issues Technical Requirements : - Bachelors or Masters degree (B.Tech/M.Tech/BE/ME) in Electrical or Electronics Engineering from a reputed institution - Minimum 4 years of hands-on experience in analog/mixed-signal IC design Proven experience in designing and delivering IPs such as : - PLLs, LDOs, Bandgap References, SerDes, ADCs/DACs - High-speed interfaces like PCIe Gen2/3/4, USB2/3, MIPI DPHY - Strong understanding of transistor-level design, device physics, and analog circuit behavior - Proficient with industry-standard EDA tools such as Cadence Virtuoso, Spectre, HSPICE, and Calibre - Experience with full-chip floor planning, IR drop analysis, EM/ESD verification is desirable - Familiarity with lab measurement tools like oscilloscopes, BERTs, and spectrum analyzers - Experience in silicon debug and post-silicon validation

Cadence Design Systems - Lead Analog Design Engineer - SoC (4-7 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position : Sr. Information Security Analyst Grade : IT3 Location : Noida/Bangalore Key Responsibilities : - Lead and implement security architecture and solutions to safeguard enterprise systems, networks, and data. - Conduct vulnerability assessments, penetration testing, and risk assessments to identify and mitigate security threats. - Develop and enforce security policies, procedures, and best practices to ensure compliance with internal standards and industry regulations. - Collaborate with cross-functional teams to design secure systems and provide guidance on secure coding practices and vulnerability management. - Continuously monitor the security landscape for new threats and ensure proactive defense mechanisms are in place. Required Skills & Qualification : - Hands-on experience in securing corporate environment. - Hands-on experience in security frameworks (NIST, ISO 27001, CIS) and experience with risk management and compliance. - Hands-on experience securing Windows (Workstations and Servers), Linux (Workstations and Servers), and Mac. - Hands-on experience conducting risk management by identifying gaps and providing strategies for mitigation. - Hands-on experience documenting vulnerability assessment results in a clear and actionable format. - Expertise in network security, firewalls, IDS/IPS, and security monitoring tools such as SIEM. - Proficiency with cloud security technologies (AWS, Azure, GCP) and securing cloud-based infrastructure. - Experience with incident response, forensics, and managing security incidents from detection to resolution. - Determines security violations and inefficiencies. - Knowledge of mergers and acquisitions. Experience : Should have relevant experience of at least 6-10 years. Qualification : - Engineering (Computers, IT) or equivalent.

Cadence Design Systems - Senior Information Security Analyst - VAPT (6-10 yrs)

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage : The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadences employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success. Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests. You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each otherevery day. JOB Responsibilities : BE/BTECH/ME/MTECH. The responsibility primarily entails leading pre and post Silicon Subsystem Prototyping, Validation and Hardware Design for Cadence High Speed SERDES Test chips. What We Do : - Pre Silicon emulation and Verification of System in NCSIM/Palladium/other Simulators. - Hardware and Subsystem Board Design for all the Projects. (HW/SW infrastructure designed within team). - Prototyping and Firmware Development for our High Speed Serdes like PCIe, CXL , UCIe, USB ,ethernet. - Lead the Bring up, Debug, Compliance efforts and System level Characterization all the way to report release. - Engage in interop and Customer Debug. What You'll Gain : - Chance to work on cutting edge SERDES IP's from Cadence. - Refer to Cadence Website for more details on our SERDES IP's. - Tremendous learning curve on SERDES PHY, Controllers, Protocol and System integration. - Hardware and Subsystem design expertise. - Experience in deploying and debugging your Solutions in different customer environments. Minimum Qualifications :. What we are looking for : - 10-15 years (with Btech) or 10 years (with Mtech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. - 2-3 years of management experience leading/mentoring a small team of engineers. - Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on PCIe/CXL/UCIe/Ethernet. - Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers. Preferred Qualifications. - Experience leading System testing efforts for SERDES solutions. - Experience in PCIe/UCIe LTSSM states is a plus. - 1-2 years of experience in FPGA Design and Schematic design. - 1-2 years of IP/SoC Physical Layer Electrical Validation experience is a plus. - Familiarity with Verilog RTL coding for FPGA, python,C/C++. - Good communication skills. - Seasoned Systems Validation engineer who can lead SERDES projects (PCIe/CXL/UCIe) and mentor Juniors.Were doing work that matters. - Help us solve what others cant.

Cadence Design Systems - Senior Principal Design Engineer - Firmware/PCI-e (10-15 yrs)

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